FIELD OF THE INVENTION
The invention relates to a method for fabricating a patterned layer, and in particular, to a method for fabricating a patterned layer in an integrated circuit.
Over the last 25 years, the storage density of DRAM (Dynamic Random Access Memory) memory modules has quadrupled from one generation to the next. However, the basic design of an elemental memory cell and the materials used to construct the memory cell have remained substantially unchanged. A DRAM memory cell includes a transistor and a capacitor that stores the charge required to represent the information, just as it did 25 years ago. The capacitor of the memory cell has electrodes made from doped silicon or polysilicon and a dielectric layer made of silicon dioxide and/or silicon nitride that is arranged between the electrodes.
To be able to reproducibly read the charge stored in a capacitor, the capacitance of the capacitor should be at least approximately 30 fF. At the same time, it has been necessary, and remains necessary, to constantly reduce the lateral extent of the capacitor, in order to be able to achieve the abovementioned increase in the storage density. These inherently contradictory demands imposed on the capacitor of the memory cell have led and continue to led to increasingly complex structuring of the capacitor (xe2x80x9ctrench capacitorsxe2x80x9d, xe2x80x9cstack capacitorsxe2x80x9d, xe2x80x9ccrown-shaped capacitorsxe2x80x9d), in order to be able to provide a sufficiently large capacitor surface despite the continually decreasing lateral extent of the capacitor. However, this makes fabrication of the capacitor increasingly complex and therefore increasingly expensive.
A further way of achieving a capacitor with a sufficient capacitance is to use different materials between the capacitor electrodes. Therefore, in recent times new materials, in particular paraelectrics and ferroelectrics, have been used between the capacitor electrodes of a memory cell instead of the conventional silicon oxide/silicon nitride. These new materials have a considerably higher relative dielectric constant ( greater than 20) than the conventional silicon oxide/silicon nitride ( less than 8). Therefore, when these materials are used to obtain the same capacitance in a memory cell with same lateral extent, the capacitor area required and therefore the complexity of the patterning of the capacitor required can be reduced considerably. By way of example, barium strontium titanate (BST, (Ba, Sr) TiO3), lead zirconate titanate (PZT, Pb(Zr, Ti) O3) or lanthanum-doped lead zirconate titanate, or strontium bismuth tantalate (SBT, SrBi2Ta2O9) are used.
In addition to conventional DRAM memory modules, ferroelectric random access memories, known as FRAMs, will play an important role in the future. Compared to conventional memory arrangements, such as for example, DRAMs and SRAMs (Static Random Access Memories), ferroelectric memory arrangements have the advantage that the stored information is not lost even when the voltage or current supply is interrupted, but rather remains stored. This non volatile state of ferroelectric memory arrangements is based on the fact that, when using ferroelectric materials, the polarization which is applied using an external electric field is substantially retained even after the external electric field has been disconnected. The abovementioned new materials, such as barium strontium titanate (BST, (Ba, Sr) TiO3), lead zirconate titanate (PZT, Pb(Zr, Ti)O3) or lanthanum-doped lead zirconate titanate, or strontium bismuth tantalate (SBT, SrBi2Ta2O9) are also used for ferroelectric memory arrangements.
Unfortunately, when these new paraelectrics or ferroelectrics are used, new electrode materials must also be used. The new paraelectrics or ferroelectrics are usually deposited on electrodes that are already present (bottom electrodes). The processing takes place at high temperatures, and at these temperatures, the materials which usually make up the capacitor electrodes, for example doped polysilicon, are readily oxidized and lose their electrically conductive properties, which would lead to a failure of the memory cell.
Because of their good resistance to oxidation and/or the formation of electrically conductive oxides, 4d and 5d transition metals, in particular platinum metals (Ru, Rh, Pd, Os, Ir, Pt), and in particular platinum itself, appear to be promising candidates that could replace doped silicon/polysilicon as the electrode material.
Unfortunately, it has been found that the abovementioned materials, which are now being employed in integrated circuits, are very difficult or even impossible to etch chemically. The material that is removed by etching, even when using xe2x80x9creactivexe2x80x9d gases, is attributable predominately or almost exclusively to the physical component of the etching.
Patterning of the materials used hitherto has generally been carried out with plasma-assisted anisotropic etching methods. In this case, physical-chemical methods are employed, in which gas mixtures including one or more reactive gases, such as for example, oxygen, chlorine, bromine, hydrogen chloride, hydrogen bromide or halogenated hydrocarbons and inert gases (e.g. Ar, He) are used. These gas mixtures are generally excited in an alternating electromagnetic field at low pressures, with the result that the gas mixture is converted into a plasma.
The positive ions of the plasma then impinge virtually perpendicularly on the layer that is to be patterned, allowing good reproduction of a mask resting on the layer that is to be patterned. Photoresists are usually used as the mask materials, since they can be patterned relatively easily by means of an exposure step and a development step. The physical component of the etching is effected by the pulsed and kinetic energy of the impinging ions (e.g. C12+, Ar+). In this way, chemical reactions
between the layer that is to be patterned and the reactive gas particles (ions, molecules, atoms, radicals) leading to the formation of volatile reaction products, are initiated or enhanced (chemical component of the etching). These chemical reactions between the substrate particles and the gas particles are responsible for the high etching selectivity of the etching process.
Since the chemical component is small or even absent when etching the above materials, in particular, when etching the electrode material, the amount of material removed from the layer to be patterned by etching is of the same order of magnitude as the amount of material removed from the mask or the underlying layer (etching stop layer). Thus, the etching selectivity with respect to the etching mask or the underlying layer is generally low (between approximately 0.3 and 3.0). Consequently, the erosion of masks with inclined flanks and the inevitable formation of bevels on the masks means that the patterning will have a low-dimensional accuracy. Furthermore, particularly when carrying out an overetching step, the underlying layer is etched to a considerable extent, and the result is sloping etched flanks which are very difficult to control. Consequently, very small electrodes (basic surface area of the electrode=F2, F=smallest feature size which can be fabricated using a defined technique) can only be produced with considerable effort.
To improve or avoid the etching of layer materials that are difficult to etch, Published European Patent Application EP 859 405 A2, Published European Patent Application EP 867 926 A1, and Published German Patent Application DE 197 03 205 A1 describe methods in which raised capacitor electrodes, selective silicide regions or combined precious metal/non-precious metal structures are formed.
It is accordingly an object of the invention to provide a method for fabricating a patterned layer in which the abovementioned problems with occur in the physical-chemical etching processes are considerably reduced or avoided altogether.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for fabricating a patterned layer from a layer material. The method includes steps of: a) providing a substrate with at least one target region and at least one migration region; b) applying a layer material; c) adding a material selected from the group consisting of Ti, TiN, Ta, TaN, W, WN, Bi, Biox, Ir, IrOx, IrHfOx, Ru, RuOx, Pd, and PdOx to the layer material; and d) performing a heat treatment such that the layer material migrates from the migration region to the target region and a layer which is self-aligned and self-patterned with respect to the target region is formed.
The method has the advantage that the layer material, which can often only be etched with difficulty, does not have to be patterned directly. The desired structure of the layer is predetermined by preliminarily structuring the substrate into a target region and a migration region, and is produced by the migration of the layer material as a result of the heat treatment, in a self-organization process. Consequently, direct etching of the layer material, with all the abovementioned problems, can be avoided.
The surface of the migration region is such that, under identical conditions, the layer material has a higher mobility at the migration region than at the target region. This ensures that the layer material flows from the migration region to the target region during the heat treatment. The surface of the migration region has somewhat unfavorable properties with regard to wetting by the layer material or with regard to its adhesion. By contrast, the target region enables good wetting and adhesion of the layer material in that region. As a result of the preliminary structuring of the substrate into a target region and a migration region, a layer consisting of the layer material which is self-aligned and self-patterned with respect to the target region is formed.
If the method is used for fabricating an electrode, for example, for a storage capacitor, the method also has the advantage that the electrode can be selected to be as small as its connection. If the connection, usually a plug with a barrier, for the electrode of a stack capacitor is fabricated with the smallest feature size F2 that can be fabricated with conventional fabrication methods, the basic surface area of the electrode has to be selected to be considerably greater than F2 to ensure an overlap between the electrode and the barrier. If, with the conventional fabrication methods, the basic surface area of the electrode were not selected to be significantly larger than F2, inaccuracies in the alignment of the corresponding masks could lead to no overlap between the electrode and the barrier. This would lead to an unconnected electrode, which would lead to a failure of the memory cell. Accordingly, memory cells in which a stack capacitor is used require relatively large amounts of space, which has an adverse effect on the storage density that can be achieved.
In the method, the connections can be used as target regions and the insulating layer which lies between the connections can be used as the migration region. Accordingly, the electrodes are formed, as part of the layer to be patterned, in a self-aligned manner on the connections (target regions) so that a sufficient overlap between the electrodes and their connections is automatically ensured. There is no need to undesirably enlarge the electrode, which is necessary in the prior art to compensate for positional errors. Accordingly, the space required by the electrode can be reduced.
Since the preliminary structuring of the substrate is used to define the structure of the layer that will be patterned, for example, for fabricating the connections of the memory cell, it is also possible to save one mask level. The different masks that are used in the prior art to produce the connections and to produce the electrodes can be combined to form a single mask so that the fabrication costs can be reduced considerably.
In accordance with an added feature of the invention, in step b), the layer material is applied as a thin film. This has the advantage that existing processes can be used to apply the layer material without requiring significant changes to the process parameters. Furthermore, it is preferable if the layer of the thin film has a thickness of less than 100 nm, preferably less than 50 nm. The atoms or molecules of the layer material then have sufficient mobility, so that the migration of the layer material is concluded within a relatively short time. If it is desirable to produce patterned layers of relatively great thickness, it is preferable if steps b) and c) are repeated, to produce a patterned layer of a predetermined thickness.
The layer thickness of the applied layer material should preferably be selected so that it is possible for the layer material to migrate to the target region. If the layer thickness is excessive, the migration may be impaired.
In accordance with an additional feature of the invention, the heat treatment is carried out at a temperature of more than 550xc2x0 C., preferably more than 600xc2x0 C. Furthermore, it is preferable if the heat treatment is carried out in an oxygen, nitrogen or argon atmosphere.
In accordance with another feature of the invention, the layer material is deposited over the entire surface by sputtering. Furthermore, it is preferred if the sputtering temperature is over 500xc2x0 C.
In accordance with a further feature of the invention, the migration region contains SiO2, Si3N4, Al2O3, AlN, BN, MgO, La2O3, LaN, Y2O3, YN, Sc2O3, ScN, TiO2, Ta2O3 or an oxide of the lanthanides, and/or the target region contains Pt, Pd, Rh, Ir, Ru, Os, Re or their conductive oxides or silicides, Cu, Ag, Au, Ni, Si, or a transition metal or a silicide of the transition metals. Furthermore, it is preferred if a metal of the 4d and 5d transition metals, in particular a platinum metal, in particular platinum, or rhenium is used as the layer material.
In accordance with a further added feature of the invention, Ti, TiN, Ta, TaN, W, WN, Bi, BiOx, Ir, IrOx, IrHfOx, Ru, RuOx, Pd and/or Pdox is added to the layer material prior to step c). In a preferred configuration, this takes place by applying a layer that contains these materials to the layer material and performing a heat treatment so that the materials diffuse into the layer material. The addition of the materials increases the mobility of the atoms or molecules of the layer material, so that the migration of the layer material is completed within a relatively short time.
In accordance with a further additional feature of the invention, the following steps are carried out in step a) to provide the substrate that has at least one target region and at least one migration region: a substrate including the material of the migration region is provided; the material of the target region is applied; and the material of the target region is patterned so that at least one target region and at least one migration region are produced.
The patterning of the material of the target region may in this case take place by using a photographic technique with subsequent etching or by using a damascene technique.
In accordance with yet an added feature of the invention, in step a), the following steps are carried out to provide the substrate that has at least one target region and at least one migration region: a substrate is provided; the material of the target region is applied; the material of the target region is patterned; the material of the migration region is applied; and a planarization step is carried out so that at least one target region and at least one migration region are produced.
In this case, it is preferred if the material of the target region is deposited as a layer and the material of the target region is patterned using a hard mask. Preferred materials for the hard mask are titanium nitride, titanium oxide or silicon oxide. Using a hard mask generally results in rounded edges during the patterning of the material of the target region. The structures that are produced in this way have a smaller lateral extent on their top side than on their underside. If the area around these structures is then filled with the material of the migration region, target regions with a lateral extent that is smaller than that which could be produced directly with the lithography employed are produced on the surface.
In accordance with a concomitant feature of the invention, the material of the migration region is also deposited as a layer.
It is particularly preferred if a CMP step is carried out as the planarization step.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in method for fabricating a patterned layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.